cml flops with small arpeture

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cml flip flop

I am trying to design a DFF with extremely small aperture. What is the best way to achieve this? In the flop, I am using the conventional latch architecture with resistive loads.
Is there a better way to do this?
Do you have any literature on improving arpeture time?

 

[ce]

Most important for the aperture in your CML flip flop is actually the rise time of the driving clock and data signals. The clock edges determine the time that's needed to switch from the buffer to the latch in the DFF (hold time). The steeper the data signals, the better the setup time. You might consider adding a peaking inductor in series with your load resistors...