dtz_lou
Newbie level 6
Hi all,
I would like to ask you two questions.
1) If the the pull-up resistor is 50 Ohm, what conditions set the bias current (current tail) of the differential pair?
I know that ISS*50 Ohm should be < Vth of the differential pair for keeping the diff. pair in saturation.
So, if I do not choose the maximum current (i.e:Vth/50 Ohm) but I rather select less current (in order to save power consumption), this would be a problem for the termination load (which is also 50 Ohm, terminates to a network analyzer)
The cml buffer is on-chip design. The input frequency is 2GHz.
2) The diff. input signal is a rail2rail voltage swing. This transient signals are coming from CMOS inveters. Is that a problem for the functionality of the diff. pair? Ideally we would like something less (ie:Vin_diff> sqrt(2)*Vov but close to that value)
Let me know if something is not clear.
Thanks
I would like to ask you two questions.
1) If the the pull-up resistor is 50 Ohm, what conditions set the bias current (current tail) of the differential pair?
I know that ISS*50 Ohm should be < Vth of the differential pair for keeping the diff. pair in saturation.
So, if I do not choose the maximum current (i.e:Vth/50 Ohm) but I rather select less current (in order to save power consumption), this would be a problem for the termination load (which is also 50 Ohm, terminates to a network analyzer)
The cml buffer is on-chip design. The input frequency is 2GHz.
2) The diff. input signal is a rail2rail voltage swing. This transient signals are coming from CMOS inveters. Is that a problem for the functionality of the diff. pair? Ideally we would like something less (ie:Vin_diff> sqrt(2)*Vov but close to that value)
Let me know if something is not clear.
Thanks