clocking how to modify this parameters in EXAMPLE DESIGN of MIG files

[hannachifaten]

hi every body , :smile:
i'm using a spartan6 (frequency of my fpga is 27mhz ) and DDR3 Performance : 800mps

For a DDR3 800 Mb/s interface with the memory clock = 400 MHz and a x8 bit
memory device:
The result is 16 bits of data transfer per clock cycle (8 bits on each clock edge)
• For a x64 bit User interface:
The user clock should be set at or above (16/64) * 400 MHz = 100 MHz
so i use my parameters like this :

constant C3_CLKOUT0_DIVIDE       : integer := [B]1[/B]; 
   constant C3_CLKOUT1_DIVIDE       : integer := [B]1[/B]; 
   constant C3_CLKOUT2_DIVIDE       : integer := [B]16[/B]; 
   constant C3_CLKOUT3_DIVIDE       : integer := [B]16[/B]; 
   constant C3_CLKFBOUT_MULT        : integer := [B]8[/B];

if that is correct or not , and i want to understand clearly these parameters ,
any responses any syggestion , pleasee :sad:

 

[syedshan]

Hi boss!

first of all if I understanding right, you have a fundamental mistake in following line

The result is 16 bits of data transfer per clock cycle (8 bits on each clock edge)

1. DDR3 transfers data in 8n burst format, where n is the data-word. Hence in you case i.e. x64 it is 8*64 = 512 bits per data transfer per WRITE CYCLE or READ CYCLE. where 1 READ or WRITE cycle consists of 2- clock cycles. Please see the image
2. Secondly this data transfer is further split into 2 cycles (read the DDR3 specification from JEDEC or your specific DDR3). for now see image below


I think this is enough for now for you to get shocked :grin:
so now you have to re-read the specs. and redesign what you have till now.

 

[hannachifaten]

thanks Man
i have to understand this how i fill it better :wink:
because it still unclear :O
good afternoon

 

[syedshan]

Hi again.

By the way when I was looking for case, I bookmark few xilinx forum's query. Mostly they are for virtex-6, but click here and there and you will get for spartan-6 as well ^^

Xilinx answers
1. User interface addressing : **broken link removed**
2. similar : http://forums.xilinx.com/t5/MIG-Mem...-incrementing-address-efficiently/td-p/129378
3. MIG virtex 6 questions : here , Virtex-6 core funtionality, burst wrapping

Hope this helps

 

[hannachifaten]

hello , have you any idea what is the meaning of these errors :
in fact these are a lot of warnings but the code didn't synthesize :

WARNING:HDLCompiler:871 - "C:\Documents \Top.vhd" Line 271: Using initial value "00000000001000011101111010111010" for n10id since it is never assigned
which my code is like this :

signal n10Id :  std_logic_vector(31 downto 0):="00000000001000011101111010111010";  --(n,Qn-5)

any suggestion and thank youuuu