# clocking block in test bench

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#### srish

##### Newbie level 6
why we define clocking block normally in interface in a test bench???? is there any significance of this??
and one more thing that if we do not define any clocking block in a test bench then also it works fine how???? is there any default input skews and output sync time ???

#### meir

##### Junior Member level 3
clocking block is useful for verification environments where you have
one task driving the signals and another sampling them.
If a clocking block isn't used and the signals are driven and sampled on the same clk edge
the signals could be sampled before they are driven (depends on how the simulator schedules the tasks)
You can write a simple test bench with 2 tasks :drive() sample() both of them :
Code:
forever begin
@(posedge clk)
......
end
fork them in the initial begin block
and see what happens

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srish

### srish

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#### dave_59

##### Advanced Member level 3
If you do not use a clocking block, then you need to synchronize and provide skews as if your testbench was another piece of RTL connected to your DUT. This is easy to understand if you do both design and verification. For the engineer just doing verification, some of the idiosyncrasies of Verilog's wires versus variables semantics can be confusing. The clocking block abstracts some of that away from the testbench writer.

See my DVCon12 paper that discusses this: **broken link removed**

srish

### srish

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#### srish

##### Newbie level 6
hey thank you ...i read out the paper i.e. how approach to verification enhanced from traditional approach regarding the interconnection between design and test bench..i will try and follow ur advice ......currently i am doing designing in a project .......vl try to co-relate the things together...
If you do not use a clocking block, then you need to synchronize and provide skews as if your testbench was another piece of RTL connected to your DUT. This is easy to understand if you do both design and verification. For the engineer just doing verification, some of the idiosyncrasies of Verilog's wires versus variables semantics can be confusing. The clocking block abstracts some of that away from the testbench writer.

See my DVCon12 paper that discusses this: **broken link removed**

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