clockgating methodology

[asicdesign]

in synopsys, power compilier can add clockgating automatically, if I have a block, there is a global enable for some DFFs, you can change the code add manually clockgating
1. what is pros and crons if you do manually clockgating vs Power compiler automatic gating?
here are more specific questions:
2. if manually add clockgating, do you have to create_generate clock on the clockgating celll output? I can see there are a lot of load for these gated clock
3. how will the Power compiler handle this scenario? I didn't see the tool automatically create_generated_clock by power compiler.
4. what is the right way to handle this scenario

 

[echoas]

When you do manually clock gating, you must be careful to the introduced skew by combinantional logic. And in sequential clock gating, make sure it is synchronous correctly. I think the Power compiler will take all the factors into consideration. If the results is the same as we think. I think the two way is same.

The gated clock is belong to the generated clock. you had better to assert it as a generated clock using the cammand create_generated_clock/

regards

 

[rca]

1- for our experience more than 10years, we design low power chip, the manual gated clock instertion is well know control than what it is done by the tool, or we do not see interesting power reduction based on our gated clock design.
2- yes, a combinational logic is added on the clock network, but the clock tree tool handle that without any issue.
3- You do not need to used create_generated_clock, how we made the gated clock is a latch+and gate, and the clock tree goes through this and gate.