pre cts setup: uncertainty = jitter+ margin+skew
post cts setup: uncertainty = jitter + margin
just as Fahmy said, The Jitter is a quantitative measure for the clock uncertainty
it's a really clock ,output of pll.osc~~~~~~
jitter will inpact the duty cycle of your clock.
so if you some path rising to falling edge or inverse, you need to increase your clock frequency by the jitter.
I mean if your design shoul run at 10MHz, the period is 100ns, but if you have fall to rise flop, you have only 50ns, if your jitter is plus or less 10%, you should expect your half period equal to 45ns instead 50ns. so the design should be synthesise at 1/90ns => 11.1MHz.
jitter is basically the uncertainty in clock edge. if we set jitter value of suppose 1ns on rising edge to a clock having on time10 ns then the rising edge can occur 1ns later therefore the ON time becomes 9 ns or it can arrive before 1 ns resulting in ON time of 11ns. hence affecting the duty cycle.
The clock uncertainty is the margin given to the clock so that ur setup or the hold window is reduced. since u need to subtract this uncertainty value.
Now as u know the Jitter is the characteristic of the oscillator. But the jitter effects only the setup and not the hold. I guess u know abt this.
So the uncertainty value pre CTS will contain = skew + jitter + margin(for OCV)
And post CTS it is = jitter + margin(for OCV)
Hope its clear.