clock uncertainty vs clock jitter

[jitendravlsi]

What is the difference between clock uncertainty and clock jitter?



thanks in advance
jitendra

 

[Fahmy]

I can't see a difference .... The Jitter is a quantitative measure for the clock uncertainty (deviation of the actual time event with respect to the time point where it shall occurs ideally)

 

[devop]

pre cts setup: uncertainty = jitter+ margin+skew
post cts setup: uncertainty = jitter + margin

just as Fahmy said, The Jitter is a quantitative measure for the clock uncertainty
it's a really clock ,output of pll.osc~~~~~~

 

[jitendravlsi]

Thanks u both Fahmy and Devop..........

 

[neetinsingh]

Following link would be of great help.....



-neetin

 

[chandrakanenator]

pre cts setup: uncertainty = jitter+ margin+skew
post cts setup: uncertainty = jitter + margin

just as Fahmy said, The Jitter is a quantitative measure for the clock uncertainty
it's a really clock ,output of pll.osc~~~~~~

Can you tell how the input delays and output delays are calculated in presence of jitter,skew and setup margin.Dont give just the formula.Its available evrywhere but it is bit hard to interpret them..

 

[nisshith]

in case of input delay we use jitter setup margin and clock frequency to calculate the input delay.
The input delay is the delay from input pin to the D pin of the flip flop.
the required time for this problem would be = clock period - Tsetup - clock jitter within this required time data should be availed on the D pin of the flip flop. on the data path there can be a existing delay because of some combinational logic (Tpd).
There for remaining time is termed as maximum input delay which is Required time - Tpd

Same analogy u can use for the o/p delay

 

[rca]

jitter will inpact the duty cycle of your clock.
so if you some path rising to falling edge or inverse, you need to increase your clock frequency by the jitter.
I mean if your design shoul run at 10MHz, the period is 100ns, but if you have fall to rise flop, you have only 50ns, if your jitter is plus or less 10%, you should expect your half period equal to 45ns instead 50ns. so the design should be synthesise at 1/90ns => 11.1MHz.

 

[nisshith]

if we consider the uncertainity while STA we don't have to increase the frequency

 

[jeet_asic]

how will it impact duty cycle ? as far as i know If it impacts duty cycle that means their r chances that it will effect setup and hold time , but i don't think so that duty cycle gets affected . Jitter is related to delaying of clock , which is somewhat similar to uncertainty .

jitter will inpact the duty cycle of your clock.
so if you some path rising to falling edge or inverse, you need to increase your clock frequency by the jitter.
I mean if your design shoul run at 10MHz, the period is 100ns, but if you have fall to rise flop, you have only 50ns, if your jitter is plus or less 10%, you should expect your half period equal to 45ns instead 50ns. so the design should be synthesise at 1/90ns => 11.1MHz.

 

[nisshith]

jeet_asic
jitter is basically the uncertainty in clock edge. if we set jitter value of suppose 1ns on rising edge to a clock having on time10 ns then the rising edge can occur 1ns later therefore the ON time becomes 9 ns or it can arrive before 1 ns resulting in ON time of 11ns. hence affecting the duty cycle.

 

[jeet_asic]

Jitter of 1ns means that your "whole" clock will be delayed by 1ns , not some edge, clock time period will remain as it is . Thats why after post-layout jitter is equal to uncertainity . Increase in jitter will effect your latency . AFAIK it won't affect duty cycle.

jeet_asic
jitter is basically the uncertainty in clock edge. if we set jitter value of suppose 1ns on rising edge to a clock having on time10 ns then the rising edge can occur 1ns later therefore the ON time becomes 9 ns or it can arrive before 1 ns resulting in ON time of 11ns. hence affecting the duty cycle.

 

[nisshith]

You can set uncertainty for specific edges affecting the duty cycle.
In Practical sense also uncertainty is measure of uncertainty in arrival of edges of particular clock entire clock can also shift if both edges arrive later but practically anything can happen. During the STA we take worst case while setup and hold check.

 

[rca]

depending how your clock is generated is not easy to say you have always 50% of duty cycle.
if the uncertainty act on both edge, ok this modelize the jitter effect.

 

[pavanks]

The clock uncertainty is the margin given to the clock so that ur setup or the hold window is reduced. since u need to subtract this uncertainty value.

Now as u know the Jitter is the characteristic of the oscillator. But the jitter effects only the setup and not the hold. I guess u know abt this.

So the uncertainty value pre CTS will contain = skew + jitter + margin(for OCV)

And post CTS it is = jitter + margin(for OCV)

Hope its clear.

 

[vijji.sami]

The clock uncertainty is the margin given to the clock so that ur setup or the hold window is reduced. since u need to subtract this uncertainty value.

Now as u know the Jitter is the characteristic of the oscillator. But the jitter effects only the setup and not the hold. I guess u know abt this.

So the uncertainty value pre CTS will contain = skew + jitter + margin(for OCV)

And post CTS it is = jitter + margin(for OCV)

Hope its clear.

how jitter affects only the setup n not hold?
plz reply me soon...

 

[rogeret]

but if you have fall to rise flop, you have only 50n

could u explain the quoted?