clock to Q delay increase in setup time

[bvpk]

Hi every body,


I just want know (In D flip flop)why does the clock to Q delay increases when D input reaches minimum setup time.

 

[lostinxlation]

Because they're related to each other through the clock delay inside a flop provided the clock delay to the master and slave latches are matching.

 

[bvpk]

hi lostinxlation,

can please elaborate little bit on it.

thanks,

 

[lostinxlation]

My suggestion is to search a transistor level circuit of D-FF on google, and analyze what would happen to setup time and clock to Q, when you delay or advance the clock arrival time.

 

[dftrtl]

By reducing the setup time requirement internally the slave latch clock is delayed. So clk --> q increases