You can have the buffer insertion in the DC to take care of the clock tree. However, the results are not as good as CTS/clock-gen in the back end. Since in the sub-micron/deep-sub-micron the wire load dominated the delay. The wire load could only be estimated after the placement.
If you just need a quick and dirty answer about the delay from clk source to the flops, please take log on your flop number and times the clock buffer delay, than times a constant (which depends on you tech and die size for wire delay).
Good luck,