Hello there,
I once did this job before. But the system I worked on with a mixed system. We implemented a phase locked loop as follows:
We needed to recover a 512kbit/sec clock, we had VCO chip and LPF out of the spartan3e chip. The phase detector and divider were implemented inside the FPGA.
Please note that for recovering 512kbit/sec clock we needed 8 or 16MHz VCO so that after division we can compare the phases between the incoming reference clock and the local VCO clock.
Therfore, your clock speed up to 150 MHZ needs special treating cause I dun think you can get a VCO up to 150 * 8 MHZ.
I highly recommend that you read xilinx application note xapp868.pdf by Paolo Novellini and Giovanni Guasti. The authors shows that Low data rates (less than 10 Mb/s) can be recovered by fully digital PLLs.
regards,
S. Yassin