Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Clock recovery problem with FSK demodulator

Not open for further replies.


Full Member level 4
Oct 6, 2002
Reaction score
Trophy points
Activity points
Clock recovery ?

I have built an FPGA-based FSK demodulator but i have a problem in clock recovery ... can any body give me a hand in this prob. Thanx

I just know some about clock recovery from NRZ or RZ format data. There are useing some dpll skill in the process.

one method

In the analog world a method that is within 1 dB of optimum is

1. Slice the base band data signal to get hard limiting
2. Low pass with a 1 pole filter at 3/8 of the bit rate
3. Square (full wave rectification will also work but is a few dB worse
4. Filter out the spectal line at the bit rate

Can this be approximated in your FPGA?

Can you design the signal format for easier clock recovery (at the expense of wider signal bandwidth)? For instance, a return to zero scheme with the frequency shifted up or down from the center represents a one or zero and comes back to the center for a short time to make the return to zero part. That way you can slice the signal up and down and know that you have the bit period completely determined.

i don't know why specialy 3/8 of the bit rate in step 2 ? but any way .. to do it digitally i think it's more easy than what u say ... just i don't know how ?!!

clock recovery

Can you explain your problem in more details. I had do some effort in my thesis. :idea:

geni answer

To answer the question by Geni, The one pole low pass filter -3 dB frequency in Hertz is equal numerically to the bit rate multiplied by the fraction 3/8. This method is mentioned in the about 20 year old satellite communications book by Spilker.

You can get some information in the attached docs.

good luck


yeah, i get some good idea from this reference

ok but ...

it's ok this pdf gives a good solution in orthogonal frequencis
but in my case ...
to be more clear
1- i am receiving BFSK
2- buad rate 1200 Hz
3- F1=1300Hz for "1" , F2=2100Hz for "0"
4- pilot stream = 01010101010...
now how can i get the true 1200 Hz from the incoming stream ! :cry:

Not open for further replies.

Part and Inventory Search

Welcome to