clock of Sigma delta modulator in fractional-N pll

[aok_fine]

Hi everyone,
In fractional N plls the divider value is dithered by a sigma delta modulator. I need to know is this sigma delta modulator is clocked by reference clock or the divider output? And Why? Also, if we had higher frequency clocks can they be used instead?
Thanks in advance

 

[josephjv86]

Hi aok_fine,

It is better to use a high frequency than reference for clocking sigma delta modulator, so that the harmonics at the feedback will be at higher frequencies . this will reduce the filter cap requirement and achieve a reasonable bandwidth & lock time.

But the sigma delta clock should be limited to a value , to allow enough clock cycles to divide the output frequency by the divider value.