With "analog" PLL, I was mainly referring to a PLL with analog VCO. I see, that the term isn't clear, in the PLL book of Roland E. Best, these PLL type is named DPLL, because it involves a digital phase detector and a digital frequency divider. The built in PLLs of recent FPGA can't process a reference frequency of 64 kHz, so it won't be an option to use them. That's why I suggested an external PLL chip.
If you want to implement the PLL in digital logic exclusively, an ADPLL (a PLL with a digital oscillator used as VCO) would be the only option. The intended output frequencies can be however derived from a single frequency divider, because all factors are simply powers of two.