Clock multiplier using ADPLL

[noura7]

Please can any one tell me how can i design an ADPLL as a clock multiplier that multiply reference frequency 64 khz to 128 khz, 512 khz and 8192 khz at the same time.

thanks a lot
Noura

 

[FvM]

Why you are asking for an ADPLL? A simple "analog" PLL chip, e.g. 74HC4046 can perform the 64 to 8192 kHz multiply. The dvided clocks will be available from the frequency divider without additional effort.

 

[noura7]

the analog PLL consume a huge area in FPGA implementation than a digital one and i use this device to clock a multirate filters respectively at 128 khz, 512 khz and 8192 khz at the same time.

"The dvided clocks will be available from the frequency divider without additional effort."

i think if i add a three parallel frequency divider in the feedback i will also use a three parallel differents VCOs.

how can i clock at the same time the multirate filters with 3 clocks derived from a fondamental clock?

thanks a lot
Noua

 

[FvM]

With "analog" PLL, I was mainly referring to a PLL with analog VCO. I see, that the term isn't clear, in the PLL book of Roland E. Best, these PLL type is named DPLL, because it involves a digital phase detector and a digital frequency divider. The built in PLLs of recent FPGA can't process a reference frequency of 64 kHz, so it won't be an option to use them. That's why I suggested an external PLL chip.

If you want to implement the PLL in digital logic exclusively, an ADPLL (a PLL with a digital oscillator used as VCO) would be the only option. The intended output frequencies can be however derived from a single frequency divider, because all factors are simply powers of two.

 

[noura7]

the goal is that i want to implement the ADPLL with the multi-rates filters on FPGA which support a maximum frequency of 500 Mhz. the probleme that with many DCOs and dividers the chip consume more area. have you an idea how can i do it or an example that help me.

thks FvM
Noura

 

[noura7]

With "analog" PLL, I was mainly referring to a PLL with analog VCO. I see, that the term isn't clear, in the PLL book of Roland E. Best, these PLL type is named DPLL, because it involves a digital phase detector and a digital frequency divider. The built in PLLs of recent FPGA can't process a reference frequency of 64 kHz, so it won't be an option to use them. That's why I suggested an external PLL chip.

If you want to implement the PLL in digital logic exclusively, an ADPLL (a PLL with a digital oscillator used as VCO) would be the only option. The intended output frequencies can be however derived from a single frequency divider, because all factors are simply powers of two.

thank you FvM. How can i use a single divider that produce a three output frequencies at the same time (not programmable) and have you a vhdl code of this divider.

thanks a lot
Noura