noura7
Member level 2

Please can any one tell me how can i design an ADPLL as a clock multiplier that multiply reference frequency 64 khz to 128 khz, 512 khz and 8192 khz at the same time.
thanks a lot
Noura
thanks a lot
Noura
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With "analog" PLL, I was mainly referring to a PLL with analog VCO. I see, that the term isn't clear, in the PLL book of Roland E. Best, these PLL type is named DPLL, because it involves a digital phase detector and a digital frequency divider. The built in PLLs of recent FPGA can't process a reference frequency of 64 kHz, so it won't be an option to use them. That's why I suggested an external PLL chip.
If you want to implement the PLL in digital logic exclusively, an ADPLL (a PLL with a digital oscillator used as VCO) would be the only option. The intended output frequencies can be however derived from a single frequency divider, because all factors are simply powers of two.