clock jitter in LVDS transmitters

[zhonghan]

lvds jitter

If the data and reference clock of the LVDS transmitter i use is very noisy. Then
How to design the corresponding receiver?
I exactly mean that how to choose the bandwidth of the clock recovery loop. If i use a very narrow loop as normal considerations, the recoved clock can not track the reference clock from the transmitter very quickly, which can result in suboptimal sampling at the receiver( fast changing data, slowly changing clock). So i tend to increase the bandwidth of the PLL in the clock recovery loop.

Is that correct ? how can i improve the jitter tolerance of the receiver when the jitter resulting from the LVDS transmitter is very large.

 

[FvM]

jitter clock

The question is, if received LVDS signals can be recovered reliable in eye-diagram. If this isn't the case, there is no way to achieve an error-free data transmission.

If the reference clock actually shows noise respectively unrelated phase jitter rather than an unstable clock frequency with related data phase jitter, small bandwith of clock recovery circuit would give better results.

 

[zhonghan]

+lvds +jitter

Our application is the LVDSR in LCD timing controller. Now whether the LVDS signal can be reliably recoverd depends on the aligning degree betwen the input signal and the recovered clock. The rising /falling edge and pulse width of the output data of the transmitter are fully determined by the synchronous clock. The phase noises of the data and clock from the transmitter are apparently related.
when we use a filtered clock (by the recovery loop) to sample a noisy data, the results is certainly not so good.
I think the low pass transfer effect will alway exists no matter which kind of topology is adopted to recover the clock (e.g. DLL / PLL based CDR) . so is it unavoidable? Increasing the bandwidth of the loop can enable the recovered clock track the input clock as the data faster, meanwhile the VCO jitter can also be suppressed ( if a PLL based CDR is adopted ).

 

[RDRyan]

oversampling data recovery circuit

Increasing the bandwith of the loop, the recoverd clock will track the input noisy clock. but whether the data can be decoder by the recoverd clock?

 

[obovolo]

+oversampling +cdr +jitter +tolerance

if ur signal is not so fast, phase picking oversampling CDR might be a good alternative.