Someone told me A & B = !(!A | !B) , but I am not sure how it is directly related to my question above since both are using CP and there is no negation in one of the inputs for the AND gate ?
By inverting CLK input the latch has to wait until next rising flange.
As you have correctly spotted in the added diagram these cells prevent ‘chopped’ clock pulses, finishing to complete clock period in case what the latch considers input data (E TE EB TEB .. whatever) ends up (or starts up) asynchronously.
May be you would gain further insight what seems to be, at least from the contents of the following link:
This paper presents a low power Clock Gating scheme for clock power improvement that reduces power dissipation by deactivating the clock signal to an inactive value (for clock gating cell) when clock is supposed to be gated (for soc). The presented circuit also overcomes the high clk-to-out...
www.design-reuse.com
the author of the diagrams used in your question, including a contact form, regarding those 2 cells not as consumption efficient as the proposed improvement.
The major difference between both gating circuits is that the clock idles low respectively high.
Using transparent latches instead of DFF brings up a risk of glitches if the enable signal toggles near one clock edge. But metastability avoidance would require to synchronize enable to clock anyway.