clock gating latches

[promach]

Could anyone help to explain why OR type Clock Gate requires positive latch ?
while AND type Clock Gate requires negative latch ?

 

[KlausST]

Hi,

I assume to avoid glitches at the output.

Is it a true transparent latch or a D-FF?

Klaus

 

[promach]

Someone told me A & B = !(!A | !B) , but I am not sure how it is directly related to my question above since both are using CP and there is no negation in one of the inputs for the AND gate ?

 

[promach]

For AND-type clock gate:

 

[JohnBG]

The only difference between the 2 clock gating latches is 1 clock cycle.

The AND cell is one clock cycle behind compared to the output of the OR cell.

D latches only ‘listen’ to the input on CLK rising.

https://www.electronics-tutorials.ws/sequential/seq_4.html

By inverting CLK input the latch has to wait until next rising flange.

As you have correctly spotted in the added diagram these cells prevent ‘chopped’ clock pulses, finishing to complete clock period in case what the latch considers input data (E TE EB TEB .. whatever) ends up (or starts up) asynchronously.

May be you would gain further insight what seems to be, at least from the contents of the following link:

Low Power High Density Clock Gate

This paper presents a low power Clock Gating scheme for clock power improvement that reduces power dissipation by deactivating the clock signal to an inactive value (for clock gating cell) when clock is supposed to be gated (for soc). The presented circuit also overcomes the high clk-to-out...

www.design-reuse.com

the author of the diagrams used in your question, including a contact form, regarding those 2 cells not as consumption efficient as the proposed improvement.

 

[promach]

The only difference between the 2 clock gating latches is 1 clock cycle.

The AND cell is one clock cycle behind compared to the output of the OR cell.

D latches only ‘listen’ to the input on CLK rising.


https://www.electronics-tutorials.ws/sequential/seq_4.html

By inverting CLK input the latch has to wait until next rising flange.

Wait, I am still confused with your "1 clock cycle" statements above.
I do not think the inverter will cause such issue.

 

[FvM]

The major difference between both gating circuits is that the clock idles low respectively high.

Using transparent latches instead of DFF brings up a risk of glitches if the enable signal toggles near one clock edge. But metastability avoidance would require to synchronize enable to clock anyway.

 

[promach]

For https://www.design-reuse.com/articles/34973/low-power-high-density-clock-gate.html , could anyone explain how the following newly proposed clock gate circuit architecture works ?

1. How does it reduces the clock-to-out path by merging the internal latch sequential loop and clock invertors ?
2. How does it saves an area of equivalent to 2 inverters ?