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clock from library pll- need clock signal in the kHz in fpga

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wanida

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clock from library pll

If I need a clock signal in the kHz in fpga, is it better for me to use Megafunctions PLL and feed then divide the onboard clock signal with a factor as high as it can go or should I keep the division factor lower and feed it through a clock divider circuit (counters)?
I just see many examples showing out of PLL into the counter so I'm just wondering if that's the way to go?

thanks
 

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