Jun 29, 2010 #1 J jeffreycui Newbie level 3 Joined May 18, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location San Jose Activity points 1,303 Hi I have some setup timing issue for clock enable signals after CTS, the problem is due to too many buffers are inserted after the clock gater, is there any way to limit the number of buffers inserted after clock gater ? I am using synopsys ICC to do the CTS. thanks
Hi I have some setup timing issue for clock enable signals after CTS, the problem is due to too many buffers are inserted after the clock gater, is there any way to limit the number of buffers inserted after clock gater ? I am using synopsys ICC to do the CTS. thanks
Jun 29, 2010 #2 itsmeteja Full Member level 2 Joined Feb 29, 2008 Messages 132 Helped 36 Reputation 98 Reaction score 21 Trophy points 1,298 Location Bangalore, India, India Activity points 2,086 You need to model the clock latency during the place opt stage for all the clock gaters.
Jun 29, 2010 #3 J jeffreycui Newbie level 3 Joined May 18, 2010 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location San Jose Activity points 1,303 The problem is not from the place opt step. The design meet setup timing at the place step. The timing is broken after cts step. Either way, please elaborate how the clock latency modeling at place opt step will help. thanks
The problem is not from the place opt step. The design meet setup timing at the place step. The timing is broken after cts step. Either way, please elaborate how the clock latency modeling at place opt step will help. thanks