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Clock enable signal timing after CTS

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jeffreycui

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Hi

I have some setup timing issue for clock enable signals after CTS, the problem is due to too many buffers are inserted after the clock gater, is there any way to limit the number of buffers inserted after clock gater ?

I am using synopsys ICC to do the CTS.

thanks
 

The problem is not from the place opt step. The design meet setup timing at the place step. The timing is broken after cts step.

Either way, please elaborate how the clock latency modeling at place opt step will help.

thanks
 

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