jeffreycui
Newbie level 3
Hi
I have some setup timing issue for clock enable signals after CTS, the problem is due to too many buffers are inserted after the clock gater, is there any way to limit the number of buffers inserted after clock gater ?
I am using synopsys ICC to do the CTS.
thanks
I have some setup timing issue for clock enable signals after CTS, the problem is due to too many buffers are inserted after the clock gater, is there any way to limit the number of buffers inserted after clock gater ?
I am using synopsys ICC to do the CTS.
thanks