sachinagg77
Member level 3
duty cycle correction circuit
I intend to design a "Clock Duty Cycle Correction Circuit" that can handle input clocks with duty cycle ranging from 20% to 80% and output a clock with 50% duty cycle [with a tolerance of 1%].
Another important requirement for the circuit is LOW JITTER performance as this circuit is meant for providing clock to high performance ADC.
I would be grateful if anyone could inform me about some relevenat reference to start the design.
Thank You
Sachin
I intend to design a "Clock Duty Cycle Correction Circuit" that can handle input clocks with duty cycle ranging from 20% to 80% and output a clock with 50% duty cycle [with a tolerance of 1%].
Another important requirement for the circuit is LOW JITTER performance as this circuit is meant for providing clock to high performance ADC.
I would be grateful if anyone could inform me about some relevenat reference to start the design.
Thank You
Sachin