I intend to design a "Clock Duty Cycle Correction Circuit" that can handle input clocks with duty cycle ranging from 20% to 80% and output a clock with 50% duty cycle [with a tolerance of 1%].
Another important requirement for the circuit is LOW JITTER performance as this circuit is meant for providing clock to high performance ADC.
I would be grateful if anyone could inform me about some relevenat reference to start the design.
hi Sachin,
I once read two papers about clock duty cycle cerrection, one is
G J.Maneatis, "Low jitter process-independant DLL and PLL based on self-biased techniques", JSSC VOL.31.NO11,1996.
the other is
J.Lee," A low-noise fast-lock phase-lock phase-locked loop with adaptive bandwidth control,JSSC VOL35.NO8,2000.
hope this will help.
If you can provide a clock at twice the frequency, then a simple flip-flop would do the trick nicely.
Otherwise you may consider the use of a PLL, whose oscillator provides a 50% duty-cycle. Alternatively, the PLL can run at twice the speed and the output can again be divided by two using a FF, for 50% duty-cycle.
Thanks VVV for the suggestions. I forgot to mention in my original message that the clock frequency required is 110MHz. As I do not have a PLL that can provide a low jitter output at this frequency, I use a crystal generator to generate the clock. Although the output of crytal generator has 50% duty cycle, it degrades on its way to the actual data converter [due to board imperfections etc]. Any further suggestions are welcome.