Clock dominates latch-type voltage sense amplifier output

[phen3x]

Hello guys. I am trying to create a voltage comparator, but in the circuit I am using the clock seems to dominate everything that happens, even the signal before the differential amplifier input. Any thoughts as to what might be going on?

 

[dick_freebird]

How you inject the clock, especially its return ground, may
be critical. For this reason I like to avoid on-board termination
in favor of inline "bullet" terminations (5V, 50 ohms is 100mA
of single ended current, against what may be a pretty resistive
and inductive PCB). Even 0.1 ohm and you may blow your input
threshold spec.

And where you place your 'scope ground, relative to all of this,
can matter too.

Now these are simple practicalities, and it's unclear whether
this is a bench reality or a computer aided exercise. If the
comparator in question exists only in schematics and simulation
then more likely the problem is elsewhere (since testbenches
tend to be ideal and free of the "which ground and how is it
different?" question).

 

[phen3x]

Indeed I am simulating with Cadence Spectre, so these practicalities don't really apply in that case.. For me the weird thing is that I even get spikes from the clock before the differential input on my input signal, while the clock is placed inside the latch comparator...

 

[D.A.(Tony)Stewart]

Show your circuit and include stray inductance, capacitance & ESR and layout.
Then show your results.