tariq786
Advanced Member level 2

I have a few questions related to CDC which may be stupid but i hope it will lead to good discussion
1) why not use two latches as syncrhonizer rather than 2 D flip flops
2) can static timing analysis detect CDC?l
3) why not use asynchronous fifo to transfer control signals and data signals together rather than sending control signals through syncrhonizer and data through asynchronous fifo.
4) how to model metastability in verilog simulation?
5) how to verify CDC path with simulation as well as formal analyses?
Thanks
1) why not use two latches as syncrhonizer rather than 2 D flip flops
2) can static timing analysis detect CDC?l
3) why not use asynchronous fifo to transfer control signals and data signals together rather than sending control signals through syncrhonizer and data through asynchronous fifo.
4) how to model metastability in verilog simulation?
5) how to verify CDC path with simulation as well as formal analyses?
Thanks