clock domain crossing. Yet another questions

[tariq786]

I have a few questions related to CDC which may be stupid but i hope it will lead to good discussion

1) why not use two latches as syncrhonizer rather than 2 D flip flops
2) can static timing analysis detect CDC?l
3) why not use asynchronous fifo to transfer control signals and data signals together rather than sending control signals through syncrhonizer and data through asynchronous fifo.
4) how to model metastability in verilog simulation?
5) how to verify CDC path with simulation as well as formal analyses?


Thanks

 

[lostinxlation]

1. if two latches are pos and neg edge, respectively, it is essentially equivalent to a single flop. Not enough.
If they are the same type, either pos only or neg only, it gets transparent and the signal that is not synchronized gets exposed to the receiving clock domain. This is virtually the same as no synchronizer.
2. probably. Especially if clock speeds are not integer multiple.
3. It's used.
4. If you turn on the timing check, it warns.
5. Just like any other simulations.

 

[dftrtl]

1. You can use latches and effectively get flop out of it.
2. No way it can detect.
3. You can
4. In GLS you can
5. By good luck we can hit these kind of paths.