clock division - using analog logic, logic in the clock path

[sharanbr]

what do divisions mean on a clock

Hi,

I have couple of questions pertaining to clocks

1) why is it necessary that one uses analog logic like pll to do a clock division when it can be done using just flops

2) why fpga technology prohibits logic in the clock path e.g. to gate the clocks

Regards,

 

[Digital-L0gik]

Re: clock division

PLLs are fancy mixed signal designs. They allow you to divide down clocks cleanly. By cleanly I mean with minimal clock skew on the output clocks. Flip Flops do not have the extra circuitry to clean up the output. Therefore, when possible use plls.

Gating clocks adds skew.

 

[sharanbr]

Re: clock division

True that gates clocks add additional skews. But that is also the case in ASIC. But the issue seems to be more than that in case of FPGAs due to which I have seen recommendations not use gated clocks.

Regards,

 

[Digital-L0gik]

Re: clock division

My other guess would be that in asics, you have the ability to add more sophisticated clock trees and so any skew in clock gating can be negligible.

 

[fpga_asic_designer]

clock division

there are at least two reasons why gates should be prevented along the clock tree from front end netlist:
1. too many gates on the clock line will typically screw up the duty cycle
2. gates will complicate CTS procedures.

It is allowed to add muxes and xor or inverters prior to the clock tree, and during the CTS for adding INV or BUF, and during the synthesis for adding clock gating logics, but otherwise, clock line should be as clean as possible.

 

[kDaniu]

Re: clock division

1) why is it necessary that one uses analog logic like pll to do a clock division when it can be done using just flops

ASIC design
using only flip-flops for the CLK dividing. the skew is not worst after dividing
BUT, effect from jitter grow up and realy more important
that is why do not recomment to use any dividings or use dividing with a synchronization (with precursor CLK)

2) why fpga technology prohibits logic in the clock path e.g. to gate the clocks

becasue of the clock propagation...

regards, Dan

 

[sameer_dlh25]

Re: clock division

1. Can you multiply clocks with digital logic ? PLL can do that.
2. Clock coming out of Flop may work at lower frequencies. For higher frequency > 50 MHZ flop based divider will distort clock duty cycle a lot.

 

[kDaniu]

Re: clock division

1. Can you multiply clocks with digital logic ? PLL can do that.

basically author asced about clock division

.... to do a clock division ...

2. Clock coming out of Flop may work at lower frequencies. For higher frequency > 50 MHZ flop based divider will distort clock duty cycle a lot.

if you read my previous post, I do not recommend any way to use divided manually clock
but if you are realy need it then flip-flop based divider has to be simpler then other for a not high frequency schemes

Regards, Dan