CLOCK DIVIDER

[__apotamkin]

I am writing a clock divider to get 10sec, 8sec, 3 sec from 50 Mhz clock signal.

This is my main module code :

---

Code Verilog - [expand]
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`timescale 1s / 1s
 
module deneme1(clock_in,red,yellow,green
    );
input clock_in; // input clock
output reg red; // output clock after dividing the input clock by divisor
output reg yellow;
output reg green;
reg[27:0] counter=28'd0;
parameter DIVISOR = 28'd2;
// The frequency of the output clocks(red,yellow,green)
//  = The frequency of the input clk_in divided by DIVISOR
// For example: Fclk_in = 50Mhz, if you want to get 1Hz signal to blink LEDs
// You will modify the DIVISOR parameter value to 28'd50.000.000
// Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz
always @(posedge clock_in)
begin
counter <= counter + 28'd1;
if(counter>=(DIVISOR-1))
  counter <= 28'd0;
red <= (counter<DIVISOR/2)?1'b1:1'b0; //if red <= (counter<DIVISOR/2) 1b'1 else 1'b0
end
 
always @(posedge clock_in)
begin
counter <= counter + 28'd1;
if(counter>=(DIVISOR-1))
  counter <= 28'd0;
yellow <= (counter<DIVISOR/2)?1'b1:1'b0;
end
 
always @(posedge clock_in)
begin
counter <= counter + 28'd1;
if(counter>=(DIVISOR-1))
  counter <= 28'd0;
green <= (counter<DIVISOR/2)?1'b1:1'b0;
end
endmodule

---

And this is the test bench code:

---

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`timescale 1s / 1s
 
module deneme1tb;
// Inputs
reg clock_in;
// Outputs
wire red;
wire yellow;
wire green;
// Instantiate the Unit Under Test (UUT)
// Test the clock divider in Verilog
deneme1 uut (
  .clock_in(clock_in),
  .red(red),
  .yellow(yellow),
  .green(green)
);
initial begin
  // Initialize Inputs
  clock_in = 0;
  // create input clock 50MHz
        [B]forever #5000 clock_in = ~clock_in;[/B]
end
     
endmodule

---

This is the simulation
I set simulation time to 50 from simulation settings and when I look at the simulation, end of the diagram is 0.000000050000s as you can see. Why it doesn't look like just 50s ? How can I fix this?

 

[ads-ee]

Your timescale is nuts. 1 second!?

You can't generate a 50 MHz clock with a timescale of 1 second

Use `timescale 1ns/10ps or something similarly smaller than 1s.

Then to generate a 50MHz clock you will need to use

---

Code Verilog - [expand]
1
forever  #10 clock_in = ~clock_in;  // toggles clock_in every 10 ns (10 intervals of 1ns from timescale *1ns* / 10ps)

---

instead of

---

Code Verilog - [expand]
1
forever #5000 clock_in = ~clock_in;  // this toggles clock_in every 5000 seconds or at 10000 second period, i.e. 0.0001 Hz

---

--- Updated Jan 26, 2021 ---

You also have counter driven by three different always blocks, I'm surprised this even compiles correctly for simulation as you've got multiple drivers on the counter signal.

It seems like you are trying to write software instead of a hardware description.

 

[__apotamkin]

Your timescale is nuts. 1 second!?

You can't generate a 50 MHz clock with a timescale of 1 second

Use `timescale 1ns/10ps or something similarly smaller than 1s.

Then to generate a 50MHz clock you will need to use

---

Code Verilog - [expand]
1
forever  #10 clock_in = ~clock_in;  // toggles clock_in every 10 ns (10 intervals of 1ns from timescale *1ns* / 10ps)

---

instead of

---

Code Verilog - [expand]
1
forever #5000 clock_in = ~clock_in;  // this toggles clock_in every 5000 seconds or at 10000 second period, i.e. 0.0001 Hz

---

--- Updated Jan 26, 2021 ---

You also have counter driven by three different always blocks, I'm surprised this even compiles correctly for simulation as you've got multiple drivers on the counter signal.

It seems like you are trying to write software instead of a hardware description.

Now the simulation looks like this

 

[ads-ee]

Then change the timescale to 1ns/1ns or change the scale so it shows the time in ns or ps.

--- Updated Jan 26, 2021 ---

You want your 2nd number in the timescale to have the same resolution (ns, ps, etc) as the waveform scale. Currently you have the waveform scale set to seconds instead of ns).

 

[__apotamkin]

Then change the timescale to 1ns/1ns or change the scale so it shows the time in ns or ps.

It did not change anything but thank you

 

[ads-ee]

With the changes I suggested here is a quick run of the files in Vivado

as you can see the setting for the time in the waveform is set to auto and shows the time as 50.00 ns as the resolution is 10ps.

--- Updated Jan 26, 2021 ---

Make sure you make both timescales the same.

 

[__apotamkin]

With the changes I suggested here is a quick run of the files in Vivado

View attachment 167171

as you can see the setting for the time in the waveform is set to auto and shows the time as 50.00 ns as the precision is 10ps.

I really don't want to bother you and If I am bothering you please stop me but I have a term project and as you can see I am not capable to do it. Do you mind If I ask for help ? Tomorrow is due time and I couldn't done half of it still. I just need to do 1 traffic light with 10sec red, 3 sec yellow and 8 sec green periods and I have 25,50,100 Mhz clock signals -I can use just one or all of them- to generate those 10,3,8 clocks. Please give me tips I am begging rn (

 

[ads-ee]

If it's due tomorrow, how long have you been procrastinating on this term project?

FYI, I'm not going to do this project for you, so if you want help ask questions on the forum, maybe I or someone else will answer.

IMO the easiest way to do this is using an FSM with 4-states: idle, red, yellow, green. You use a counter to determine when you leave the red, yellow, and green states (10s, 3s, and 8s respectively). You can use the same counter with different terminal counts you compare to for the state's exit condition. You'll have to figure out what to do after green or what starts the FSM from idle.

 

[FvM]

Did you even read the comment you copied along with the example code?

// You will modify the DIVISOR parameter value to 28'd50.000.000
// Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz

You really should modify the code...

To generate three different blink frequecies in one module, you need three separate counter variables and DIVISOR parameters. A more elegant solution could be to instantiate the module three times with different frequency parameters.