clock divider jitter
Thanks for the responses. My question regarding jitter effects has the following reason:
I was wondering whether multi-rate cascaded (MASH) sigma delta modulators might benefit from a slower clock in the first stage and higher clock in the second stage VS. a 2nd order modulator single loop at a high clock rate.
I mean, if the clock rates are chosen such, that under ideal conditions the two modulators would give the same performance, which one do you think might work better in light of jitter.
Any comments?
Cheers