clock divider - jitter

[svensl]

divider jitter

I was wondering:

I have a system clock with total jitter J1 and then divide the clk-frequency down by a factor of M, does this mean I divide my J1 also by M?

Can someone shed some light on this?

Thanks a bunch.

 

[brmadhukar]

effect of jitter on divider clocks

Jitter is variation in cycle to cycle period. If you divide, you are not changing the absolute jitter. But Jitter/Time period decreases.

BRM

 

[Fahmy]

effect on jitter with clock divider

If you are using a ripple counter in your divider then the jitter will be accumulated. But If you are using a synchronus counter jitter in the output of the divider will be the same as that in the input assuming that the circuits are noiseless.

 

[svensl]

clock divider jitter

Thanks for the responses. My question regarding jitter effects has the following reason:

I was wondering whether multi-rate cascaded (MASH) sigma delta modulators might benefit from a slower clock in the first stage and higher clock in the second stage VS. a 2nd order modulator single loop at a high clock rate.

I mean, if the clock rates are chosen such, that under ideal conditions the two modulators would give the same performance, which one do you think might work better in light of jitter.

Any comments?

Cheers