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clock definitions and timing constraints...(dc - synopsys)

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ee1

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after defining the clock,
is what are the timing constraints i must define?

Regards,
 

chipseller

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Do you mean:

define_clock {Clock} -freq 100 -clockgroup default_clkgroup_0 -rise 0 -fall 5 -route 5
Which would be typical of the input constraint file for Synopsis (Scope source file)

or create_clock -period 10.000000 -waveform {0.000000 5.000000} Clock
which is a typical sdc file format - in both cases the frequency and duty cycle are declared in nS
 

ee1

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i mean the "create_clock..."
 

chipseller

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create_clock -period 10.000000 -waveform {0.000000 5.000000} <Clock>

Period speaks for istelf the two parameters in the waveform switch set the rising and falling edges, thereby setting the duty cycle and <clock> is substituted for your own signal name. SDC does not allow for any other parameters to be entered
 

ee1

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ok,
i realize the confusion now...
my question was refering to the sdc file...
i have done some reading and i think its clear now...
thanks.
 

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