mahshidkardan
Newbie level 4
Hi,
I have designed a 10-bit pipeline ADC and now I am trying to arrange gain stages around the clk generator(on the layout) in a way that the stages which should be synchronized, receive the clk at the same time. I do not know how much latency causes the distance between clk and gain stages on the layout and if this distance can affect the clk synchronization or not. I did not find any document on the web related to this problem. Would you please let me know about it if you have any information or references?
Thank you in advance
I have designed a 10-bit pipeline ADC and now I am trying to arrange gain stages around the clk generator(on the layout) in a way that the stages which should be synchronized, receive the clk at the same time. I do not know how much latency causes the distance between clk and gain stages on the layout and if this distance can affect the clk synchronization or not. I did not find any document on the web related to this problem. Would you please let me know about it if you have any information or references?
Thank you in advance
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