casex (mysig)
1'b0: y <= 1'b0;
1'b1: y <= 1'b1;
endcasex
You should read the document more carefully.There is no case option with the enable in unknown state. So how can it erroneously match one of the case items?
What Permute stated is exactly what the attached document implies.permute
You need to read carefully what I asked. What you stated does not match to what is claimed in page no. 9 of attached document, in the third paragraph. It has been claimed that:
What does the second paragraph in page no. 10 try to mean?
do you really understand what x is, and what casex does ? Unknown is unknown, not 0, not 1. No you aren't correct.Ok an 'x' can be any value like '0', '1' or any non logical voltage level. In this exapmle in the attached paper in page no. 9 one of the case items will match if enable is unknown and this unknown is '1'. It will not match any case items if this unknown is zero or any non-logical vale. Am I correct?
you don't get x with pre-synthesis, but get x with post-synthesis and you can catch the initiizalization issue.But what does this sentence "In the pre-synthesis
design, this might mask a reset initialization problem that would only be visible in post-synthesis
simulations." in the third paragraph in page number 9 mean?
Condition doesn't match, then x propagates.I also do not understand what does the last sentence in first paragraph in page no. 9 ". The equivalent post-synthesis simulation will propagate ‘X’s through the gate-level
model, if that condition is tested." mean?
Completely misunderstood what X is. There is no such interpretation like unknown is 1 or unknown is 0. Unknown is unknown.The 'x' is unknown. It can be eith '1' or '0' or any other voltage value not representing '0' or '1'. In your example if mysignals is 'x' and that 'x' is '0' then , it will match the first case option and if the unknown is '1', then it will match the second case option. Is not it?
Regards
You have not understood that there is a difference between simulation and a real circuit. For simulation, 'X' is a separate value which is different from both '0' and '1'. This means that casex works like you think only in simulation.I am confident about my understanding of casex. For casex, the synthesis tool synthesizes the netlist in such an way that even if there is unknown, it will land up to a known value because of casex where casesx always prduces known outputs against unknown inputs.
This means that casex works like you think only in simulation.
See, in a real chip when we drive the inputs with real signals, the signals can be '0' or '1' or a voltage value which is neither '1' nor '0'. This voltage value which is neither '1' nor '0' is unknown. In reality for signals there is no value called 'x'. The 'x' is a voltage value which is neither '1' nor '0'. Sometimes in one particular input the signal that should come should be always '1' but it may wrongly be driven '0'. In that case '0' is unknown. Correct me if I am wrong.
This understanding is not correct either. If you get unknown inputs, you can easily get 'x' on outputs of the netlist regardless of that it's from casex, or case. When the netlist generated from 16 bit case items in casex gets 0xXXXX as an input, do you think the netlist can generate a known value on the output with the simulation ? Please tell me what kind of synthesis tool does it.I am confident about my understanding of casex. For casex, the synthesis tool synthesizes the netlist in such an way that even if there is unknown, it will land up to a known value because of casex where casesx always prduces known outputs against unknown inputs.
Read the document you attached VERY CAREFULLY. It clearly explains gate level simulation and casex dont' match in certain situation and it even showed the example code.lostinxlation
I am talking of simulatio at gate level. How will 'x' be propagated in simulation at gate level?
If I use casex, then gate level simulation should also match with RTL simulation. Why is noy it so?
lostinxlation
I HAVE ANOTHER QUESTION
If we use casex, then there should not be any simuation and synthesis mismatch. Because the synthesis tool will synthesize the gate level netlist in such a way so that for an unknown input the output will be a known state. Please provide explanation to correct me if I am wrong here. I find that the attached paper in this case talks of simulation and synthesis mismatch for using casex and casez. But why?
In the same attached document at page no. 9 in third paragraph it writes "In the pre-synthesis design, this might mask a reset initialization problem that would only be visible in post-synthesis simulations." How is it possible? Because the synthesis tool when synthesizes the given code it will synthesize the gate level netlist in such a way that it produces one of those three outputs even with unknown as inputs. Is not IT?
You wrote "This understanding is not correct either. If you get unknown inputs, you can easily get 'x' on outputs of the netlist regardless of that it's from casex, or case. When the netlist generated from 16 bit case items in casex gets 0xXXXX as an input, do you think the netlist can generate a known value on the output with the simulation ? Please tell me what kind of synthesis tool does it. "
.
How is it possible ?
OK, why don't you create a netlist equivalent to the code provided in the document, put X on the input, and see what happens by yourself instead of asking question ? It won't take 15 minutes to find the answer.
Well, you are not understanding the theoretical part of this, that's why you need experiment by yourself. If you refuse to make your hands dirty, good luck in your career.
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