Binome
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OK, thanks for the link.
Here is my new code:
What I understand is that full is '1' only if someone tried to write and couldn't. What I'd like is full to prevent someone to write because it would be impossible.
Here is my new code:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ring_fifo is
generic(
fifo_length : integer:=8;
fl_bits : integer := 3;
data_width : integer:=4);
port(
clk : in std_logic;
rst : in std_logic;
ren : in std_logic;
wen : in std_logic;
dataout : out std_logic_vector(data_width-1 downto 0);
datain : in std_logic_vector(data_width-1 downto 0);
empty : out std_logic;
err : out std_logic;
full : out std_logic);
end ring_fifo;
architecture arc of ring_fifo is
type memory_type is array (0 to fifo_length-1) of std_logic_vector(data_width-1 downto 0);
signal memory : memory_type := (others => (others => '0'));
signal readptr,writeptr : unsigned(fl_bits-1 downto 0) := to_unsigned(0, fl_bits);
signal full0 : std_logic := '0';
signal empty0 : std_logic := '1';
begin
full <= full0;
empty <= empty0;
err <= '1' when (empty0='1' and ren='1') or (full0='1' and wen='1')
else '0';
fifo0: process(clk,rst)
begin
if rst='1' then
memory <= (others => (others => '0'));
readptr <= to_unsigned(0, fl_bits);
writeptr <= to_unsigned(0, fl_bits);
full0 <= '0';
empty0 <= '1';
elsif rising_edge(clk) then
if (wen='1' and full0='0') then
memory(to_integer(writeptr)) <= datain ;
writeptr <= writeptr+1;
end if;
if (ren='1' and empty0='0') then
dataout <= memory(to_integer(readptr));
readptr <= readptr+1;
end if ;
if (writeptr+1=readptr) and (wen='1') and (ren='0') then
full0 <= '1';
else
full0 <= '0';
end if;
if (readptr=writeptr) and (ren='1') and (wen='0') then
empty0 <= '1';
else
empty0 <= '0';
end if;
end if;
end process;
end arc;