Binome
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ring_fifo is
generic(
fifo_length : integer:=8;
fl_bits : integer := 3;
data_width : integer:=4);
port(
clk : in std_logic;
rst : in std_logic;
ren : in std_logic;
wen : in std_logic;
dataout : out std_logic_vector(data_width-1 downto 0);
datain : in std_logic_vector(data_width-1 downto 0);
empty : out std_logic;
err : out std_logic;
full : out std_logic);
end ring_fifo;
architecture arc of ring_fifo is
type memory_type is array (0 to fifo_length-1) of std_logic_vector(data_width-1 downto 0);
signal memory : memory_type := (others => (others => '0'));
signal readptr,writeptr : unsigned(fl_bits-1 downto 0) := to_unsigned(0, fl_bits);
signal full0 : std_logic := '0';
signal empty0 : std_logic := '1';
begin
full <= full0;
empty <= empty0;
err <= '1' when (empty0='1' and ren='1') or (full0='1' and wen='1')
else '0';
fifo0: process(clk,rst)
begin
if rst='1' then
memory <= (others => (others => '0'));
readptr <= to_unsigned(0, fl_bits);
writeptr <= to_unsigned(0, fl_bits);
full0 <= '0';
empty0 <= '1';
elsif rising_edge(clk) then
if (wen='1' and full0='0') then
memory(to_integer(writeptr)) <= datain ;
writeptr <= writeptr+1;
end if;
if (ren='1' and empty0='0') then
dataout <= memory(to_integer(readptr));
readptr <= readptr+1;
end if ;
if (writeptr+1=readptr) and (wen='1') and (ren='0') then
full0 <= '1';
else
full0 <= '0';
end if;
if (readptr=writeptr) and (ren='1') and (wen='0') then
empty0 <= '1';
else
empty0 <= '0';
end if;
end if;
end process;
end arc;
if (rst = '1') or (ren = '1') then
full0 <= '0';
elsif (writeptr+1=readptr) and (wen='1') then
full0 <= '1';
end if;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ring_fifo is
generic(
fl_bits : integer range 2 to 15 := 3; -- log2(fifo_length)
data_width : integer range 1 to 32 := 4);
port(
clk : in std_logic;
rst : in std_logic;
ren : in std_logic;
wen : in std_logic;
dataout : out std_logic_vector(data_width-1 downto 0);
datain : in std_logic_vector(data_width-1 downto 0);
empty : out std_logic;
err : out std_logic;
full : out std_logic);
end ring_fifo;
architecture arc of ring_fifo is
type memory_type is array (0 to 2**fl_bits-1) of std_logic_vector(data_width-1 downto 0);
signal memory : memory_type := (others => (others => '0'));
signal readptr,writeptr : unsigned(fl_bits-1 downto 0) := to_unsigned(0, fl_bits);
signal full0 : std_logic := '0';
signal empty0 : std_logic := '1';
begin
full <= full0;
empty <= empty0;
err <= '1' when (empty0='1' and ren='1') or (full0='1' and wen='1')
else '0';
fifo0: process(clk,rst)
begin
if rst='1' then
memory <= (others => (others => '0'));
readptr <= to_unsigned(0, fl_bits);
writeptr <= to_unsigned(0, fl_bits);
full0 <= '0';
empty0 <= '1';
elsif rising_edge(clk) then
if (wen='1' and full0='0') then
memory(to_integer(writeptr)) <= datain ;
writeptr <= writeptr+1;
end if;
if (ren='1' and empty0='0') then
dataout <= memory(to_integer(readptr));
readptr <= readptr+1;
end if ;
if (writeptr+1=readptr) and (ren='0') and (wen='1') then
full0 <= '1';
else
full0 <= '0';
end if;
if (readptr+1=writeptr) and (wen='0') and (ren='1') then
empty0 <= '1';
else
empty0 <= '0';
end if;
end if;
end process;
end arc;
In 2.2 of the document I posted the extra pointer bits are for when you want to actually use all the locations in the FIFO. It's usually more resource efficient to allow the full condition to be one less than the depth, thereby avoiding the extra pointer logic. So for a 1024 deep memory you would have a full condition when 1023 data writes have occurred without any reads. i.e. the write pointer is at address 1023 and the read pointer is at 0 (so full is the write pointer one away, increment, from the read pointer and empty is the write pointer equal to the read pointer).in the document of the link I can read in 2.2 that the pointers have to contain an extra bit to know if the fifo is full or empty and that was the use of my 'rcycle' and 'wcycle' signals. So I think I have to reintroduce them.
Comments added below to your code. For the proper logic, refer to what I posted in my last post@K-J
I'm not sure about the new code:
Code:if (writeptr+1=readptr) and (ren='0') and (wen='1') then full0 <= '1'; else ---------------------------------------------------------------- -- KJ: The problem is that you'll get to this code whenever wen is 0. Consider the following scenario: -- 1. ren is always 0 -- 2. wen is 1 up until the fifo fills up and then shuts off and stays 0 -- Obviously now the fifo has been filled up (but not overflowing). Since the read signal is never -- set to 1, the fifo will remain full (ignoring a reset). Now let's look at what your logic does: -- In #2, on the write cycle where the writeptr is about to wrap around equal the readptr, you will set -- full to 1 with the 'if' condition that you have (so that is good). But on the very next clock cycle, #2 says -- that wen will then shut off and stay 0. So now the 'if' condition is no longer true and you end up in this -- 'else' branch which will set full to 0. But nothing has been read out, so the fifo is still full so full should -- be set to 1. -- In the code that I posted previously, it works because of the following true statements: -- Full can never be set to 1 if ren is also 1 -- Full can change from 1 to 0 only if ren is also 1 -- The same principles apply to generating the empty signal. ---------------------------------------------------------------- full0 <= '0'; end if;
No you should not@vGoodtimes
3.) Now the generics have limits and I don't understand the DMEM and BRAM matter. Shouls I use the (others => (others => '0')) or not?
You should not use two processes, vGoodtimes gave you poor advice.4.) I don't understand where I could use two processes.
Unregistered outputs can be done easily with a single process and some external assignments, but you would want to be avoiding this anyway.
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