I'm interested in designing an ASIC for a wireless data acquisition system that will operate at 5.8Ghz. I'm not sure how to determine which process to use for this design. Could someone suggest a few processes that would be a good choice for this design. I've read a couple of papers on 5.8Ghz VCO design and they used the 1P6M standard CMOS process. Are there any other processes that would work? Would any of the processes from MOSIS work for this design?
Also, could someone explain what I'm looking for in terms of material properties. Do I want a process that gives me a large gm or a small gm, what are the major factors in an IC that would lower the Q factor, what material properties play a significant role in adding HF parasitics?
ask you another question, i want to simulater a inductor's L and Q ,
someone said inductor L=imag (-1/Y(1,2)/2/PI/freq(Hendry) Q=imag(-Y(1,2)/real(Y(1,2))
with to port. but i don't konw how to structure a simulating circuit and how to set up the parameters in this circuit,
can you give me some details about it ?
thanks!
khouly said:
BICMOS sure will give higher performance in contrast with high cost
ask you another question, i want to simulater a inductor's L and Q ,
someone said inductor L=imag (-1/Y(1,2)/2/PI/freq(Hendry) Q=imag(-Y(1,2)/real(Y(1,2))
with to port. but i don't konw how to structure a simulating circuit and how to set up the parameters in this circuit,
can you give me some details about it ?
thanks!
khouly said:
BICMOS sure will give higher performance in contrast with high cost
connect the inductor in series with a current source , and use AC analysis to simulate the output between source and inductor , then using calculator in the simulator , Q=imag(Vout)/real(Vout)
L=imag(Vout)/(2*pi*xval(Vout)