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Guest
Guest
Dear all,
As you know we can use the following config. [Gray-Hurst, 4th ed. Chap. 12] to have more CLC (single-ended CM out. Cap.) than CLD (SE-DM out. Cap.), noting more lower nondominant poles in CM loops than DM loop in a feedback config., then to compensate CMFB loop at high-gain high-bandwidth spec.
however, what's your ideas to implement a (CMOS) inverting Amp. as shown in the fig. not to have any effective disadvantage on the specifications of system (except, power diss.)?:?:
really, I expressed this we have a challenging topic and we reach to a hot concept!:!:
Thanks in advance for your favor
Regards, SAZ
As you know we can use the following config. [Gray-Hurst, 4th ed. Chap. 12] to have more CLC (single-ended CM out. Cap.) than CLD (SE-DM out. Cap.), noting more lower nondominant poles in CM loops than DM loop in a feedback config., then to compensate CMFB loop at high-gain high-bandwidth spec.
however, what's your ideas to implement a (CMOS) inverting Amp. as shown in the fig. not to have any effective disadvantage on the specifications of system (except, power diss.)?:?:
really, I expressed this we have a challenging topic and we reach to a hot concept!:!:
Thanks in advance for your favor
Regards, SAZ