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[SOLVED] chain propagation of carry (help)

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pocho

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I made a testbench, which reads two vectors A and B from files and sends them to an adder which in turn sends me the sum and the carry.
Now I have to calculate the maximum length of the chain propagation of carry-overs (in the code from line 70 to 85), but I get the following errors:

** Error: C :/ test / testbench.vhd (72): No feasible entries for infix operator "/ =".
** Error: C :/ test / testbench.vhd (72): No feasible entries for infix operator "/ =".
** Error: C :/ test / testbench.vhd (72): Bad expression in left operand of infix expression "&".
** Error: C :/ test / testbench.vhd (72): Bad expression in right operand of infix expression "&".
** Error: C :/ test / testbench.vhd (72): Type error resolving infix expression "&" as type std.STANDARD.BOOLEAN.
** Error: C :/ test / testbench.vhd (75): near "=": syntax error
** Error: C :/ test / testbench.vhd (81): near "loop": expecting IF
** Error: C :/ test / testbench.vhd (86): near "elsif": expecting END

this is the code:

Code:
ibrary ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use IEEE.std_logic_textio.ALL;
    use std.textio.all; -- utilizzo del file txt

entity testbench_adder_32bit is
    generic (T0: time:= 10 ns;
             period: time:= 150 ns);
    port (
       A, B: out std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32); -- li setto a 0
       Cin: out std_logic := '0';
       S: in std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32);
       Cout: in std_logic := '0'
    );
end testbench_adder_32bit;


architecture testbench_carry_select_adder_32bit of testbench_adder_32bit is
    type test_vector_type is array (0 to 9) of std_logic_vector (31 downto 0);
    signal j: integer := 0; 
		signal k: integer := 0; 
		signal c: integer := 0;
    signal max_carry_chain: integer := 0;
		signal semaforo: integer := 0;
    signal reference_clock: std_logic := '0';
    signal T0_clock: std_logic := '0';
    signal T0_Cout: std_logic := '0';
    signal T0_reg: std_logic_vector (31 downto 0) := conv_std_logic_vector(0,32);
    signal test_vector_1: test_vector_type;
    signal test_vector_2: test_vector_type;
    signal test_vector_length: integer := 0;
		signal A_carry, B_carry: std_logic_vector(31 downto 0):= conv_std_logic_vector(0,32);
    --signal A_carry, B_carry:test_vector_type;
    begin 
        reference_clock <= not reference_clock after period/2.0;
        T0_clock <= transport reference_clock after T0;
        
        
    read_values: process
             file fp: text open read_mode is "Addizione.vhd";
             variable ln: line;
             variable x, y: std_logic_vector (31 downto 0);
             variable i: integer := 0;
             begin    
								 
                 while not endfile( fp )  loop --fatta modifica Menichelli
                     readline( fp, ln );
										 read( ln, x );
										 read( ln, y );
                     test_vector_1(i) <= x;
                     test_vector_2(i) <= y;
                     i := i+1;
										 end loop;
                 test_vector_length <= i;
             wait;
     end process read_values;
     
     
     input_generator: process (reference_clock)
        begin
            if reference_clock'event and reference_clock = '1' then
                if j < test_vector_length then
                     A <= (test_vector_1(j));
                     B <= (test_vector_2(j));
										 A_carry <= (test_vector_1(j));
										 B_carry <= (test_vector_2(j));
                     j <= j+1;
--------------------------------------------------------------------------------------------
                     for k in 0 to 31 loop														
                           if      ((A_carry(k)/= 0)) & ((B_carry(k)/= 0)) then						 
                                   semaforo<=1;											
                                   c <=c+1;										  
                           elsif     ((A_carry(k)== 1) or (B_carry(k)== 1)) & semaforo then					
                                     c <=c+1;										 
                           else
                                     semaforo<=0;
                                     c <=0;										   
                           end if;
                     end loop;
                     if max_carry_chain < c then									
	                      max_carry_chain<=c;
	                   end if;	
--------------------------------------------------------------------------------------------
                elsif j = test_vector_length then
                    j <= j+1;
                	end if;
            		end if;
        end process input_generator;

        
        
        --output_check: process (reference_clock)
               --begin
                   --if reference_clock'event and reference_clock='1' then
                      -- ASSERT (S = S_ref ) REPORT "Attenzione uscite diverse!" SEVERITY FAILURE;
                 --  end if;
        --end process output_check;
        
        
        --output_at_T0: process (T0_clock)
        --begin
            --if T0_clock'event and T0_clock = '1' then
                --T0_reg <= S;
                --T0_Cout <= Cout;
            --end if;
        --end process output_at_T0;
        
        
        write_result: process( reference_clock )
        file fpo: text open write_mode is "test_result.txt";
        variable lno: line;
        variable xo: bit_vector(31 downto 0);
        variable yo: std_logic;
        begin

            if reference_clock'event and reference_clock = '1' then
                if j/=0 and j<=test_vector_length then
                    xo := to_bitvector( S );
                    write( lno, xo );
                    writeline( fpo, lno );
										yo := Cout;
                    write( lno, yo );
                    writeline( fpo, lno );
                end if;
            end if;
        end process write_result;

end testbench_carry_select_adder_32bit;

please help me
 

I tried but it does not solve

- - - Updated - - -

I can not solve this:

Error: C:/prova/testbench.vhd(75): No feasible entries for infix operator "and".
** Error: C:/prova/testbench.vhd(75): Type error resolving infix expression "and" as type std.STANDARD.BOOLEAN.
** Error: C:/prova/testbench.vhd(114): VHDL Compiler exiting


in these lines:

elsif ((A_carry(k)= '1') or (B_carry(k)= '1')) and semaforo then

Code:
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use IEEE.std_logic_textio.ALL;
    use std.textio.all; -- utilizzo del file txt

entity testbench_adder_32bit is
    generic (T0: time:= 10 ns;
             period: time:= 150 ns);
    port (
       A, B:   out  std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32); -- li setto a 0
       Cin:    out  std_logic := '0';
       S:      in   std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32);
       Cout:   in   std_logic := '0'
    );
end testbench_adder_32bit;


architecture testbench_carry_select_adder_32bit of testbench_adder_32bit is
    type test_vector_type is array (0 to 9) of std_logic_vector (31 downto 0);
    signal j: integer := 0; 
		signal k: integer := 0; 
		signal c: integer := 0;
    signal max_carry_chain:       integer := 0;
		signal semaforo:              std_logic :='0';
    signal reference_clock:       std_logic := '0';
    signal T0_clock:              std_logic := '0';
    signal T0_Cout:               std_logic := '0';
    signal T0_reg:                std_logic_vector (31 downto 0) := conv_std_logic_vector(0,32);
    signal test_vector_1: test_vector_type;
    signal test_vector_2: test_vector_type;
    signal test_vector_length:    integer := 0;
		signal A_carry, B_carry:      std_logic_vector(31 downto 0):= conv_std_logic_vector(0,32);

    begin 
        reference_clock <= not reference_clock after period/2.0;
        T0_clock <= transport reference_clock after T0;
        
        
    read_values: process
             file fp: text open read_mode is "Addizione.vhd";
             variable ln:   line;
             variable x, y: std_logic_vector (31 downto 0);
             variable i:    integer := 0;
             begin    
								 
                 while not endfile( fp )  loop --fatta modifica Menichelli
                     readline( fp, ln );
										 read( ln, x );
										 read( ln, y );
                     test_vector_1(i) <= x;
                     test_vector_2(i) <= y;
                     i := i+1;
										 end loop;
                 test_vector_length <= i;
             wait;
     end process read_values;
     
     
     input_generator: process (reference_clock)
        begin
            if reference_clock'event and reference_clock = '1' then
                if j < test_vector_length then
                     A <= (test_vector_1(j));
                     B <= (test_vector_2(j));
										 A_carry <= (test_vector_1(j));
										 B_carry <= (test_vector_2(j));
                     j <= j+1;
--------------------------------------------------------------------------------------------
                     for k in 0 to 31 loop														
                           if      ((A_carry(k)= '1')) and ((B_carry(k)= '1')) then						 
                                   semaforo <='1';											
                                   c <=c+1;										  
                           elsif     ((A_carry(k)= '1') or (B_carry(k)= '1')) and semaforo then					
                                     c <=c+1;										 
                           else
                                     semaforo<='0';
                                     c <=0;										   
                           end if;
                     end loop;
                     if max_carry_chain < c then									
	                      max_carry_chain<=c;
	                   end if;	
--------------------------------------------------------------------------------------------
                elsif j = test_vector_length then
                    j <= j+1;
                	end if;
            		end if;
        end process input_generator;

       
       
        
        write_result: process( reference_clock )
        file fpo: text open write_mode is "test_result.txt";
        variable lno: line;
        variable xo: bit_vector(31 downto 0);
        variable yo: std_logic;
        begin

            if reference_clock'event and reference_clock = '1' then
                if j/=0 and j<=test_vector_length then
                    xo := to_bitvector( S );
                    write( lno, xo );
                    writeline( fpo, lno );
										yo := Cout;
                    write( lno, yo );
                    writeline( fpo, lno );
                end if;
            end if;
        end process write_result;

end testbench_carry_select_adder_32bit;
 

New code, new errors. Keep on learning VHDL!

Code:
elsif ((A_carry(k)= '1') or (B_carry(k)= '1')) and semaforo then

Left side of AND is boolean, right side is std_logic. Can't work.

Try:
Code:
elsif ((A_carry(k)= '1') or (B_carry(k)= '1')) and (semaforo = '1') then
 

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