In VHDL, been trying to configure the cellular ram to operate in page read mode but to no avail.. I am using the digilent nexys board.. It is working well in the asynchronous mode..
I wrote to the configuration register and did a read array for the initial startup.. and tested by writing values to consecutive addresses and tried reading it.. but the last word i read is still the initial value..
Are you saying that the specifications of the cellular ram are not within standards? I abide by the timing diagrams and gave a lot of attention to the critical timing requirements. Should i give more allowance when i output the control signals?
Currently, i wrote a set of values in consecutive locations and i am reading intermittent values.
Are you saying that the specifications of the cellular ram are not within standards? I abide by the timing diagrams and gave a lot of attention to the critical timing requirements. Should i give more allowance when i output the control signals?
Currently, i wrote a set of values in consecutive locations and i am reading intermittent values.
oh, i can not give comment cos I dont see your timing, you maybe can download the example simulations from Micron's website, the ZIP package contains simulation model and a simple testbench. I ran it in Modelsim sometime ago and it was alright.