I'm just wondering why authors used transsistors having different parameters. Such configuration have some advantages in terms of operational banwdwidth or what ?
Although you raised this issue in the Analog section, it certainly belongs to the Analog Integrated Circuit scope. That being the case, these are not exactly different discrete transistors, they are all on the same chip but just different dimensions. By the way, one of the main reasons for this is the proper biasing, given the voltage and current requirements given at each node of the circuit.
Ok, but I don't get it... I mean, why - if this is case where biasing is most significant, why they haven't use two transistors with the same sizes ? I'm wondering how this solution works in higher frequencies (?).
Because in analog IC design, you do not pick up identical transistors to adjust their biases, but rather to change their geometry to trim the dimensions of these transistors - thus making them different - in order to meet the given requirements defined by the above boundary conditions ( current "Ib", signal bias input "Vin", upper transistor bias "Vbias"). If you really want to know the effect on frequency of this "assymetry" review the gain expression or do a KCL analysis.
In many basic CMOS IC technologies you could not tie
the two FETs' bodies separately to their local source as
shown, because Psub! is global. Only a triple-well or
SOI flow (or discretes) will enable what's shown.
So given the inevitable body effect you might then size
the "guard" transistor up to make its Vgs(op) less of a
headroom-killer (maybe to the tune of half a volt?).