Capless LDO design stability problem

[marcelom]

capless ldo

I am doing an capless (&cap) LDO CMOS design, and I'm having stability issues.
DOes anyone done or have information on using NMC on an LDO which needs
to be stable with and without an output cap ?

In my current design I have an error amp followed by a +gm part that drives
the pass transsitor to the output. I have a miller cap between the output and the output of the errroramp for the dominant pole; however, the devices still oscillates in transient. It seems I need another cap, but where ?

thanks,
Marcelo

 

[santi001]

ldo and cap design

difficult to comment without looking at the architecture.
Also mention the load current.

 

[PaloAlto]

ldo design

Please, post (some) schematic, bode plots and transient response

 

[rock_zhu]

ldo stability schematic

yes. plz attach the shcematic.
You should take care of the SR when make use of NMC architecture.