[SOLVED] Can't synthesize with Synopsys Design Compiler when setting parameters in Verilog

[Konze]

Hello there,

I have the following Verilog modules which I would like to synthesize with the Synopsys Design Compiler:

PARENT

module PARENT();

    wire in;
    wire out;

    CHILD #(
        .negate(1)
    ) child (
        .in(in),
        .out(out)
    );

endmodule

CHILD

module CHILD(
    in,
    out
);

    parameter negate = 1;

    input in;
    wire in;

    output out;
    wire out;

    SUBCHILD #(
        .negate(negate)
    ) subchild (
        .in(in),
        .out(out)
    );

endmodule

SUBCHILD

module SUBCHILD(
    in,
    out
);

    parameter negate = 1;

    input in;
    wire in;

    output out;
    wire out;

    generate
        if(negate == 1) begin
            assign out = ~in;
        end
        else begin
            assign out = in;
        end
    endgenerate

endmodule

When I set negate in PARENT to 1 I'm able synthesize the PARENT module with CHILD and SUBCHILD without any problems with the Synopsys Design Compiler.
However, when I set negate in Parent to 0 I get the following error message during synthesis:

Processing 'PARENT'
Information: Building the design 'CHILD' instantiated from design 'PARENT' with
	the parameters "negate=0". (HDL-193)
Warning: Cannot find the design 'CHILD' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'CHILD' in 'PARENT'. (LINK-5)

Why isn't it possible to change the parameter to a value other than the default for synthesis with the Synopsis Design Compiler?

Best regards

konze

 

[dpaul]

Are you trying to pass down the parameter from the top-level? Please recheck as to how you are passing the parameter (I wouldn't do it the way you have shown for the .v codes for the modules CHILD and SUBCHILD).

Also be careful about the compile order of the files.

 

[ads-ee]

Unless I'm mistaken doing this Verilog 2001 sytle instantiation:

    CHILD #(
        .negate(1)
    ) child (
        .in(in),
        .out(out)
    );

with this type of antiquated module port declaration will cause errors.

module CHILD(
    in,
    out
);

    parameter negate = 1;

    input in;
    wire in;

    output out;
    wire out;

Haven't you heard of Verilog 2001 it's been around for 16 years.

Either change your module declaration to Verilog 2001 or go back to the antiquated (bad) practice of using defparam.

defparm child.negate = 1;
    CHILD child (
        .in(in),
        .out(out)
    );