Cant get one code line..

[SweetMusic]

le

 

[ring0]

The greatest bit of "address" will be 0, and the other bits will be equal to corresponding bits of "ir".

 

[FvM]

Basically, the right side expression is using three syntax elements: a constant, a concatenation and a part select. If you want to use Verilog, you should learn the basic syntax elements, either from a text book or a good reference manual.

The Synopsys HDL compiler manual is good one, to my opinion:

 

[SweetMusic]

thx

 

[FvM]

you didn't really answered to my question

As the first point, I found that the question has been sufficiently answered by ring0. As the second, it's a very basic Verilog expression, you really should learn the syntax.