qwerty_asdf
Member level 4
Well prolem is what is mentioned.
In my code i read 32bit data from a file, and store them in a ram of 8 bits datas (and 4 more times indexes.) In behavioral it works perfectly. But in place and route my ram stays always in 00000000. The result it the same either if i implement my own ram or create one with coregen.
Here is my code with some comments:
where mem_data is the data passed to filter_1, and mem_address the address to write in filter_1 memory.
From my place and route simulation those signals get the right value.
Here is the part of my filter_1 code.
and here are some warnings I get in ISE.
Here os the code of my ram_3.
In my code i read 32bit data from a file, and store them in a ram of 8 bits datas (and 4 more times indexes.) In behavioral it works perfectly. But in place and route my ram stays always in 00000000. The result it the same either if i implement my own ram or create one with coregen.
Here is my code with some comments:
Code:
component filter_1_1 is
generic
(data_length :integer := 8;
address_length:integer:=7 ;
comp_num:integer:=4;
total_number:integer:=2);
port ( clk:in std_logic;
--vin:in std_logic;
rst:in std_logic;
----------------------------------------------------------------------------
mem_data:in std_logic_vector(data_length-1 downto 0);
set: in std_logic;
mem_address: in std_logic_vector(address_length downto 0);
wea: in std_logic;
finished:in std_logic; --when L it stills sends data to filter, when H data send.
----------------------------------------------------------------------------
dout: out std_logic_vector(3*data_length-1 downto 0);
done: out std_logic
);
end component;
component rom1 IS
GENERIC
(
ADDRESS_WIDTH : integer := 7;
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data : IN std_logic_vector(31 DOWNTO 0);
write_address : IN std_logic_vector(7 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(31 DOWNTO 0)
);
end component;
signal input_data: std_logic_vector(31 downto 0);
----------------------------------------------
begin
reading_from_file: rom1 generic map(ADDRESS_WIDTH=>total_number, DATA_WIDTH=>3*data_length) port map(clk,input_data,address,wea_controller,temp_data);
passing_to_filter: landmark_1
generic map(
data_length=>data_length,
address_length=>address_length,
comp_num=>comp_num,
total_number=>total_number
) port map (
clk=>clk,
--vin=>vin,
rst=>rst,
mem_data=>mem_data,
set=>set,
mem_address=>mem_address,
wea=>wea,
finished=>finished,
temp=>temp,
--------------------------------------
dout=>dout,
temp_in_1=>temp_in_1,
temp_in_2=>temp_in_2,
temp2_sum=>temp2_sum
---------------------------------------
);
dout_temp<=mem_data;
core_address<=mem_address;
dout_res<=temp;where mem_data is the data passed to filter_1, and mem_address the address to write in filter_1 memory.
From my place and route simulation those signals get the right value.
Here is the part of my filter_1 code.
Code:
component ram3 IS
GENERIC
(
ADDRESS_WIDTH : integer := 7;
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
write_address : IN std_logic_vector(7 DOWNTO 0);
read_address : IN std_logic_vector(7 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
);
end component;
data_read_1: ram3 generic map(ADDRESS_WIDTH=>total_number, DATA_WIDTH=>data_length) port map(clk,din,address_A,address_A,wea_1,out_temp);
address_A<=mem_address;
din<=mem_data;
wea_1<='1';and here are some warnings I get in ISE.
Code:
Xst:1432 - Contents of array <ram_block> may be accessed with a negative index, causing simulation mismatch.
Xst:1433 - Contents of array <ram_block> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.Here os the code of my ram_3.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ram3 IS
GENERIC
(
ADDRESS_WIDTH : integer := 7;
DATA_WIDTH : integer := 8
);
PORT
(
clock : IN std_logic;
data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
write_address : IN std_logic_vector(7 DOWNTO 0);
read_address : IN std_logic_vector(7 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
);
END ram3;
ARCHITECTURE rtl3 OF ram3 IS
--TYPE RAM IS ARRAY(0 TO 2 ** (ADDRESS_WIDTH + 2)) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
TYPE RAM IS ARRAY(0 TO 255 ) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
SIGNAL ram_block : RAM;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(to_integer(unsigned(write_address))) <= data;
--ram_block(write_address) <= data;
END IF;
q <= ram_block(to_integer(unsigned(read_address)));
--q <= ram_block(read_address);
END IF;
END PROCESS;
END rtl3;