If the handle wafer is biased to most negative (as
would be expected for P material) then the NWell
need only be above that most-negative potential.
If the handle P- is biased to highest supply then
you'd have to externally bias the NWell even
higher, through a resistor or inductor and apply
modulation signal via a blocking capacitor
(think "Bias T") .
How you would access the local NWell, you'd
have to look over the PDK and determine - some
SOI flows include an "access via" through the
device layer and BOX, some do not.
It might be that there is no "device" corresponding
to the below-BOX DNW, or for a FET which includes
a DNW instead of Psub as its "inherited connection"
for body-substrate, S/D-substrate parasitics. Again
this is for you to investigate. You might have to
make your own subcircuit with a real FET, a
parallel "generic" FET (for the back channel) and
pcapacitors / presistors to emulate the circuit action
-and- get close to expressing connectivity.
It would be swell if you were provided a dual gate
(front and back) FET primitive with appropriate
terminals, but sometimes the road ends before
your journey does. Then you get to "cut trail".