Canceling out the parasitic diode in Layout

[hosseineslahi7]

Dear All,

I have designed a circuit in 22nm FDSOI technology which can offer
frequency modulation if a bias is applied on the back-gate of a NMOS
(HVTNFET model). In this layout, consequently, I should use deep NWELL
to separate global substrate and local substrate of that particular
transistor with body bias. Following this approach, I should draw an
NWELL ring around this Tr and connect it to Vdd otherwise the parasitic
diode between local pwell and deep NWELL cause the total power
consumption to increase incredibly.

My question is how I can have access to the nwell ring in schematic
view? I have created an NPLUS contact on top of nwell ring and introduce
a pin for it but I do not know how I should introduce such a pin in the
schematic. This pin is needed to connect nwell ring to a new bias voltage. In addition, although there is an extra pin in layout
compared to the schematic, LVS cannot realize this pin and is always clean.

I appreciate any assistance in this regard.

Cheers,

Hossein

 

[dick_freebird]

The DNWell -is- the modulation input "pin"
and it can be biased anywhere between
0 and VDD. But you'd have to punch a hole
in the BOX to access it and probably connect
with a sinker (VNW?) implant depending on
how deep the device layer and BOX stack up.

 

[hosseineslahi7]

The DNWell -is- the modulation input "pin"
and it can be biased anywhere between
0 and VDD. But you'd have to punch a hole
in the BOX to access it and probably connect
with a sinker (VNW?) implant depending on
how deep the device layer and BOX stack up.

Dear Dick,
Thank you for your answer. However, the voltage over DNWEL should be greater than the Vdd of the circuit. For this reason, I should have access to this layer and connect it to an external voltage. In this case, a new pin is needed in both the layout and schematic because of LVS restrictions. The question is how I can have access to DNWell in the schematic and pass LVS then.

Regards,

 

[dick_freebird]

If the handle wafer is biased to most negative (as
would be expected for P material) then the NWell
need only be above that most-negative potential.

If the handle P- is biased to highest supply then
you'd have to externally bias the NWell even
higher, through a resistor or inductor and apply
modulation signal via a blocking capacitor
(think "Bias T") .

How you would access the local NWell, you'd
have to look over the PDK and determine - some
SOI flows include an "access via" through the
device layer and BOX, some do not.

It might be that there is no "device" corresponding
to the below-BOX DNW, or for a FET which includes
a DNW instead of Psub as its "inherited connection"
for body-substrate, S/D-substrate parasitics. Again
this is for you to investigate. You might have to
make your own subcircuit with a real FET, a
parallel "generic" FET (for the back channel) and
pcapacitors / presistors to emulate the circuit action
-and- get close to expressing connectivity.

It would be swell if you were provided a dual gate
(front and back) FET primitive with appropriate
terminals, but sometimes the road ends before
your journey does. Then you get to "cut trail".

 

[Dominik Przyborowski]

The question is how I can have access to DNWell in the schematic and pass LVS then.

Simply use hvtnfettw device

 

[hosseineslahi7]

Simply use hvtnfettw device

Hi Dominik,
Thank you for your reply. The problem was solved by using HVTNFETTW.

Cheers

--- Updated Mar 19, 2021 ---

If the handle wafer is biased to most negative (as
would be expected for P material) then the NWell
need only be above that most-negative potential.

If the handle P- is biased to highest supply then
you'd have to externally bias the NWell even
higher, through a resistor or inductor and apply
modulation signal via a blocking capacitor
(think "Bias T") .

How you would access the local NWell, you'd
have to look over the PDK and determine - some
SOI flows include an "access via" through the
device layer and BOX, some do not.

It might be that there is no "device" corresponding
to the below-BOX DNW, or for a FET which includes
a DNW instead of Psub as its "inherited connection"
for body-substrate, S/D-substrate parasitics. Again
this is for you to investigate. You might have to
make your own subcircuit with a real FET, a
parallel "generic" FET (for the back channel) and
pcapacitors / presistors to emulate the circuit action
-and- get close to expressing connectivity.

It would be swell if you were provided a dual gate
(front and back) FET primitive with appropriate
terminals, but sometimes the road ends before
your journey does. Then you get to "cut trail".

Thank you again,

I followed your solution but I changed a bit the structure of extra circuit in my schematic. The problem is solved now. In addition, Dominik suggested a more straightforward solution here.

Thank you again.