Can you help me to analyze this circuit

[Jenifer_gao]

Hi All:

I am doing an analysis of a readout circuit for cmos image sensor, which is shown in the attachment. By controlling the reset and signal transmission gate, the reset signal and photo signal can pass to the C1 at the different time. If we assume that the transistor above the C2 is firstly turned on by applying an amp_reset, and then de-active. The reset transmission gate is turned on later. Finally the signal transmission gate is turned on. As shown in the attachment the final output of this circuit is: Vreset - Vsignal
and it satisfies:

Vreset - Vsignal = (C1/C2)(signal - reset) + ref

I tried to derive this equation, but I failed, if anybody can show me how to get it. Thanks.

Jenifer

 

[flatulent]

Something is not right in the schematic. The two analog transmission gates are in parallel and so one is redundant. Perhaps one should go to ground instead of the signal input.

 

[radiohead]

I agree. Moreover, this needs to be a switched capacitor circuit. Otherwise offset currents will nuke the opamp annex Gm stage.

 

[hanjiemy]

I think it looks like a integral ADC cell.
t1 t2 C1 C2 ref...wait

 

[cetc1525]

this is a interesting schematic.it can reduce the offset of input.

 

[amraldo]

u r using correlated douple sampling technique
there is no problem in using the two transmission gates as they operate indifferent times
ur circuit is a negative gain amplifier
it will be better if u send timing diagrams of input & output

 

[eda4you]

I've designed one time a sc int with two switches (transmission gates) in parallel. The reson was to speed up settle time (both switches on) and after the fast settling phase the one got off while the other switch (the smaller one) is still on. after some time it got also off. The reason for this strange design was to decrease charge injection (the smaller the w*l of the transistor the smaller the effect)