Hi guys
i have a pci core and some logic implement in my fpga. there is some kind of memory overwritting problem so i want to debug it. some garbage value is being written at a particular address. i dont know from where it is comming. when i test it in simulation it dosnt show any garbage value being written. it gives exact result as per the logic. so i am trying to debug this problem.
I dont have a logic analyzer. so can i use chipscope for it. If so how can i use it. Please let me know.
yes !
you can use ChipScope For your design , but Chipscope need block memory in xilinx FPGA for store data , you can set trigger in FPGA with chipscope
Chipscope is sort like a logic analyzer. The most inconvenient part is that you will have to re-compile your design, and sometimes it breaks the timing. Other than that, chipscope behaves just like a logic analyzer. You don't actually need a logic analyer to see the result of the chipscope. It displays the waveform in your PC.
Chipscope can capture the internal signals or the port on FPGA by JTAG interface, but which will spend more block memory in FPGA, because the memory will be used store the captured signals. If you have enough space in FPGA and only capture the signals on FPGA, you can use it as a logic analyzer, you set trigger condition and the memory deep.
At the same time, altera signaltab have the same function.
But i think the trigger conditions are limited in chipscope. as well the capture clock shall be internal fpga clock. so sometime the measurements are not correct and accurate compared to logic analyer.
Yes, the capture clock is also a problem, but I think you can get a high-speed clock from the PLL in FPGA, for example, if your system work at 50MHz, you can use a 100MHz or more higher clock from PLL use as the capture clock.
heloo
do u hav pci code in verilo/vhdl..
can u mail it to me on swappy.best@gmail.com,.
or anything thing which you hav related to pci bridge....
its an my acadamic project
I am having a problem with chipscope.I am unable to see some signals(which i need to analyse ) even though whole program is synthesied. (like when i go for modify connects part,i am unable to find some signals in that box where we have to slect for triggering purpose.).Can anyone tell me why..and how can i resolve this problem.