well, you can use tr primitives.I will actually design an SRAM, the whole SRAM Circuit including its sense amp, write circuit, read circuit, decoders, etc.
What I am having problems with is that I don't know all the blocks of the whole SRAM. I know some but I don't know the corresponding digital circuits. Example is the attached photo. I don't have any idea what to use instead of those access transistors. I mean all of my references were analog implementation. I don't have any reference that I could refer upon for me to design.
O.K. This refers to registers and combinational logic. No room for transistor level design, sense amplifiers and similar analog stuff.The problem is I should design the SRAM in purely digital.
Verilog has pmos and nmos primitives. You can use them if it's a fully digital circuit where the sizing is not important, however, some circuits are highly dependent on the transistor size which you can not specify in verilog and may not work. RAM cells are one of those things that tr size is important for and also a keeper with a feedback inverter will make most of the logic simulator fail to work.Is it possible to design a SRAM transistor lever circuit in verilog :???: Can you please tell me how can we approach it. I never tried it :|
The switch level modelling feature of Verilog adds if fact another interpretation of the said ambiguous question. It's neither an option for synthesis, but possibly a way to model a RAM circuit near to the real transistor level implementation.Verilog has pmos and nmos primitives. You can use them if it's a fully digital circuit where the sizing is not important, however, some circuits are highly dependent on the transistor size which you can not specify in verilog and may not work.