Can we implement or design SRAM in pure digital using verilog?

[ajhunt18]

Can we implement or design SRAM in pure digital using verilog?

I want to design an SRAM using verilog. Is it possible? Thank You!

 

[kalyanasv]

SRAM is only a device typically, made with a 6 transistors. You can use it using Verilog but not design it. you can model it using SPICE.

 

[ajhunt18]

So do you mean I can still implement SRAM in verilog? I am having problems in translating the analog components into digital or finding a corresponding digital circuits to it.

I am actually having a thesis about SRAM, and I'm using Verilog for designing it. Can't I design SRAM in pure digital?

 

[FvM]

Of course, you can design SRAM in Verilog, but what's the purpose? It's often done in simulation to represent external RAM. Synthesizing SRAM in hardware would be only reasonable in special cases, e.g. a few SRAM bits in an ASIC design. Programmable logic has usually internal hardware RAM, that can be used in a design.i

 

[lostinxlation]

if you want, you can implement exactly the same circuit(minus tr size) as SRAM with Verilog.. i.e. using structural model, but whether it can be simulated accurately is questionable.

 

[kalyanasv]

To answer your question of implementations using SRAM. yes

When you mention design an SRAM: When it comes to modifying transistor size as mentioned above you need dig deeper you have to look at cadence tools then for device modelling of the sram performance with sense amplifier,etc.. you can spice.

Forgot to mention: medici or centauraus (Synopsys) for the transistor device model for a SRAM.

This is typically done since SRAMs are very homogenous structures and can be optimized for their symmetrical structure.

SRAM's are typically digital but it all depends what you want to design. i) design an SRAM cell ii) design it peripheral circuitry iii)use the SRAM cell in an application

 

[ajhunt18]

I will actually design an SRAM, the whole SRAM Circuit including its sense amp, write circuit, read circuit, decoders, etc.

What I am having problems with is that I don't know all the blocks of the whole SRAM. I know some but I don't know the corresponding digital circuits. Example is the attached photo. I don't have any idea what to use instead of those access transistors. I mean all of my references were analog implementation. I don't have any reference that I could refer upon for me to design.

 

[FvM]

The design of the RAM cell itself can't be done in a digital hardware description language like Verilog. It's transistor level analog design. In an ASIC design enviroment, you usually have the option to interface analog circuit parts with digital blocks, that are implemented based on standard library elements.

 

[lostinxlation]

I will actually design an SRAM, the whole SRAM Circuit including its sense amp, write circuit, read circuit, decoders, etc.

What I am having problems with is that I don't know all the blocks of the whole SRAM. I know some but I don't know the corresponding digital circuits. Example is the attached photo. I don't have any idea what to use instead of those access transistors. I mean all of my references were analog implementation. I don't have any reference that I could refer upon for me to design.

well, you can use tr primitives.
BUT again, I don't think you can simulate it since typical logic simulators don't handle a timing loop.
Forget about verilog and write a spice netlist manually.

 

[ajhunt18]

Okay. The problem is I should design the SRAM in purely digital. Meaning have to find digital counterpart circuits of the analog circuits of SRAM. For example, the decoders, sense amp (or any alternative), write and read circuits, etc., I should code all of them in verilog because that's what I proposed to do. :sad:

---------- Post added at 21:20 ---------- Previous post was at 21:10 ----------

Also, what do you mean by "a few SRAM bits in an ASIC design"?

 

[FvM]

The problem is I should design the SRAM in purely digital.

O.K. This refers to registers and combinational logic. No room for transistor level design, sense amplifiers and similar analog stuff.

Post #7 actually told something different, I think the first point will be to clarify your objectives.

 

[lostinxlation]

Your question is very ambiguous. What do you actually mean by "designing SRAM in verilog" ?

Does it mean you want to design SRAM transistor level circuit in verilog, or SRAM model that behaves like SRAM on interface level, or you want to make it synthesizeable ?
We still don't get what you are trying to achieve.

 

[sam33r]

Is it possible to design a SRAM transistor lever circuit in verilog :???: Can you please tell me how can we approach it. I never tried it :|

 

[lostinxlation]

Is it possible to design a SRAM transistor lever circuit in verilog :???: Can you please tell me how can we approach it. I never tried it :|

Verilog has pmos and nmos primitives. You can use them if it's a fully digital circuit where the sizing is not important, however, some circuits are highly dependent on the transistor size which you can not specify in verilog and may not work. RAM cells are one of those things that tr size is important for and also a keeper with a feedback inverter will make most of the logic simulator fail to work.

 

[FvM]

Verilog has pmos and nmos primitives. You can use them if it's a fully digital circuit where the sizing is not important, however, some circuits are highly dependent on the transistor size which you can not specify in verilog and may not work.

The switch level modelling feature of Verilog adds if fact another interpretation of the said ambiguous question. It's neither an option for synthesis, but possibly a way to model a RAM circuit near to the real transistor level implementation.

RAM models from manufacturers are in contrast purely behavioural with timing.